JPH0586870B2 - - Google Patents

Info

Publication number
JPH0586870B2
JPH0586870B2 JP59158687A JP15868784A JPH0586870B2 JP H0586870 B2 JPH0586870 B2 JP H0586870B2 JP 59158687 A JP59158687 A JP 59158687A JP 15868784 A JP15868784 A JP 15868784A JP H0586870 B2 JPH0586870 B2 JP H0586870B2
Authority
JP
Japan
Prior art keywords
gate
bus line
thin film
drain
tft
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59158687A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6139579A (ja
Inventor
Yasuhiro Nasu
Satoru Kawai
Kenichi Yanai
Atsushi Inoe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15868784A priority Critical patent/JPS6139579A/ja
Publication of JPS6139579A publication Critical patent/JPS6139579A/ja
Publication of JPH0586870B2 publication Critical patent/JPH0586870B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates

Landscapes

  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP15868784A 1984-07-31 1984-07-31 薄膜トランジスタマトリックスアレイの製造方法 Granted JPS6139579A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15868784A JPS6139579A (ja) 1984-07-31 1984-07-31 薄膜トランジスタマトリックスアレイの製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15868784A JPS6139579A (ja) 1984-07-31 1984-07-31 薄膜トランジスタマトリックスアレイの製造方法

Publications (2)

Publication Number Publication Date
JPS6139579A JPS6139579A (ja) 1986-02-25
JPH0586870B2 true JPH0586870B2 (en]) 1993-12-14

Family

ID=15677157

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15868784A Granted JPS6139579A (ja) 1984-07-31 1984-07-31 薄膜トランジスタマトリックスアレイの製造方法

Country Status (1)

Country Link
JP (1) JPS6139579A (en])

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0691252B2 (ja) * 1986-11-27 1994-11-14 日本電気株式会社 薄膜トランジスタアレイ
JPH02109341A (ja) * 1988-10-19 1990-04-23 Fuji Xerox Co Ltd 薄膜トランジスタの製造方法
JPH04111322A (ja) * 1990-08-30 1992-04-13 Stanley Electric Co Ltd 薄膜トランジスタの製造方法
JPH04111323A (ja) * 1990-08-30 1992-04-13 Stanley Electric Co Ltd 薄膜トランジスタの製造方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58173847A (ja) * 1982-04-07 1983-10-12 Matsushita Electric Ind Co Ltd 素子作製方法
JPS5922030A (ja) * 1982-07-28 1984-02-04 Matsushita Electric Ind Co Ltd マトリクス表示パネルの製造方法
JPS5942584A (ja) * 1982-08-31 1984-03-09 シャープ株式会社 マトリツクス型液晶表示装置
JPS60261174A (ja) * 1984-06-07 1985-12-24 Nippon Soken Inc マトリツクスアレ−

Also Published As

Publication number Publication date
JPS6139579A (ja) 1986-02-25

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Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term